Intel Options

Use this window to control the Intel options.

Direct Connect Interface

Controls the Intel PCH Direct Connect Interface.

Processor Power Limit1

PL1 Power Limit in Watts. The value may vary from 0 to Fused Value. If the value is 0, the fused value is programmed. A value greater than fused TDP value is not programmed.

ME EOP Enable

Controls the ME EOP message.

ME CBD Enable

Enables or disables the ME CBD message.

Mem FlowsExt2

Enables(1) or disables(0) memory training steps in MRC flow; TX_DQDQS_PRE_DFE-BIT0; TX_DQDQS_POST_DFE-BIT1; DCA_DUTY-BIT2; RCD_DCA_DFE-BIT3; RX_DQDQS_PRE_DFE_BIT4; RX_DQDQS_POST_DFE_BIT5; TX_PERIODIC_RETRAIN-BIT6; CA_SLEW_RATE-BIT7; DCA_TCO-BIT8; E_REQ_CLK-BIT9; TURNAROUND_TRAIN-BIT10; RX_DFE-BIT11; TX_DFE-BIT12; DQ_SLEW_RATE-BIT13; DB_DFE-BIT14.

Mem FlowsExt3

Enables(1) or disables(0) memory training steps in MRC flow; RCD_DCS_DFE-BIT0; LRDIMM_BACKSIDE_TX_PER_TXN-BIT1; PATTERN_CHECKOUT-BIT2; RX_PER_BIT_DESKEW-BIT3; CA_TIMING_SIMPLE_PATTERN-BIT4; CA_VREF_COMPLEX_PATTERN-BIT5; RD_DQDQS_POST_DFE_LATE-BIT9.

Memory I/O Health Check

Auto Select option Auto for default values.
Manual Manual for new values.
Disabled Disable for disabling feature.

Pmic Secure Mode

Controls the Pmic Secure Mode.

Pmic Failure Isolation

Controls the Pmic Failure Isolation.

Memory POR

Controls the Memory POR frequency and Memory POR stretch goal.

Memory Population POR

Controls the Memory Population POR.

UMA Based Clustering

UMA Based Clustering options include Disable(ALL2ALL), Hemisphere(two cluster), and Quadrant (four cluster). These options are only valid when SNC is disabled. If SNC is enabled, UMA-Based Clustering is automatically disabled by BIOS.

Embedded SATA Test Mode

Enables or disables the Test Mode for SATA ports of the embedded SATA controllers.

S4 Support

Enables, disables, or allows normal platform control (Auto) of S4 Sleep State Support.

Embedded SATA RSTe Debug

Controls Hot Plug for SATA ports of the embedded SATA controllers.

MRC Serial Debug Output

Controls the RC/MRC Serial debug output

Disable IMC Smbus Write

Enables or disables IMC Smbus Write.

Memory RMT

Enables or disables Memory RMT.

Memory Throttling Mode

Configures Thermal Throttling Mode.

MEMHOT INPUT

Configures Memhot input.

MEMHOT OUTPUT

Configures Memhot output.

MRC Promote Warnings

Determines if MRC warnings are promoted to system level.

Promote Warnings

Determines if warnings are promoted to system level.

MemTest

Enables or disables the memory test during normal boot.

Self-Refresh Programming

Controls Self-Refreshing Programming to auto or manual mode.

CKE Throttling

Multi-Threaded MRC

Controls and executes the Memory Reference Code multi-threaded.

RX DFE DDR5 Training

Enables or disables the RX DFE DDR5 Training step.

TX DFE DDR5 Training

Enables or disable the TX DFE DDR5 Training step.

System Fast Boot

When the option is set to Enabled, portions of memory reference code are skipped when possible to increase boot speed.

Memory Test On Fast Boot

Enables or disables the memory test during fast boot.

PCH NDC Configuration Speed

Controls the configuration speed for PCH NDC device.

IO Margin Test

Controls the margin test for UPI, DMI, UpLink, and PCIe links.

IO Margin Test for Retimer Adapter

Controls the margin test for retimer adapter.

EV DFX Features

Enables or disables DFX for margining. When the option is set to Enabled, TXT and VT are disabled. When the option is set to Enabled, CScript error injection is enabled.

Disable BIOS Done

Suppresses notifying processor via MSR 151 h that boot initialization is finished.

Runtime EOM Support

When set to Enabled, Boot Guard Profile overrides in DXE phase according to current PCH/CPU combinations.

PCIe PHY test mode

Enables or disables the PCIe PHY test mode.

PCIe Live Error Recovery

Enables or disables the PCIe Live Error Recovery (LER).

Set CXL Header Bypass

Enables or disables the CXL header bypass.

Set CXL Security level

Fully Trusted CXL device can get access on CXL for host-attached and device-attached memory ranges in the WB address space.
Partially Trusted CXL device can get access on CXL for only device-attached memory ranges.
Untrusted All requests on CXL are canceled by the host.

CXL Type 3 Legacy

Enables or disables CXL type 3 device using CXL type 2 flow.

Protocol Auto Negotiation

Gen4 Only Gen4 controller only.
Gen5 Gen5 with or without mix mode.
Protocol Auto Negotiation Auto select
Force CXL There is no training discovery, the attached device must also support this mode.

DCPMM Memory Bandwidth Boost (MBB)

Enables or disables the DCPMM Memory Bandwidth Boost.

DCPMM MBB Max Supported Max Power Limit

Displays maximum supported MBB Max Power Limit value that is supported by DCPMM DIMMs in the system. This value is the largest max limit that is retrieved from the DIMMs in the system. If one DIMM reports 16,000 mW and another reports 17,500 mW, then a value of 17,500 mW is reported.

DCPMM MBB Max Power Limit

Displays the value in milliwatt granularity. Minimum value is 15000 mW. If the entered value is not a multiple of 250 mW, then BIOS internally rounds down to the nearest 250 mW alignment.

DCPMM MBB Max Supported Average Power Time Constant

Displays maximum supported MBB Average Power Reporting Time Constant that is supported by DCPMM DIMMs in the system. This value is the largest max average power reporting time constant that is retrieved from the DIMMs in the system. If one DIMM reports 100,000 ms and another reports 55,000 ms, then a value of 100,000 ms is reported.

DCPMM MBB Average Power Reporting Time Constant Step

Displays MBB Average Power Reporting Time Constant Step that is required for MBB Average Power Reporting Time Constant setting. This value is the largest average power reporting time constant step that is retrieved from the DIMMs in the system. If one DIMM reports a 2000 ms step and another reports a 500 ms step, then a value of 2000 ms is reported.

DCPMM MBB Average Power Time Constant

Displays the value in millisecond granularity. A value that is not a multiple of the MBB Average Power Reporting Time Constant Step is rejected by the FW on a DCPMM DIMM.

DCPMM Max Supported Average Power Limit

Displays maximum supported average power limit that is allowed by DCPMM DIMMs in system. This value is the largest max average limit that is retrieved from the DIMMs in the system. If one DIMM reports 16,000 mW and another reports 17,500 mW, then a value of 17,500 mW is reported.

DCPMM Average Power Limit

Displays the value in milliwatt granularity. Minimum value is 10000 mW. If entered value is not a multiple of 250 mW, then BIOS internally rounds down to the nearest 250 mW alignment.

Memory Paging Policy

Controls Memory Paging Policy.

Intel HW Memory Test

Enables or disables the memory test during normal boot.

MemTest Loops

Number of memory test loops during normal boot. Set to 0 (decimal) to run MemTest infinitely.

Allow Untested Memory for DXE Drivers

Enabled Sets the TESTED flag for all memory in PEI, making it available for DXE drivers usage.

Debug Advanced MemTest

Enables or disables ADR debug options.

Debug ADR

Enables or disables ADR debug options.

AEP Workarounds

Enables or disables workarounds for AEP sightings.

AEP Average Power Budget

Select AEP Average Power Budget (must be an increment of 250 mW).

1-ch Way in 2-2-2 Config for FM AEPs

Enabled Forces 1-ch way in 2-2-2 config for DDRT(FM) DIMMs.
Disabled Does three-way channel interleaving in 2-2-2 config for DDRT(FM) DIMMs.

Pcode WA for SAI PG

Controls Pcode work around for SAI Policy group for A Step.

NVMe OOB Presence Detect

Enables or disables Out Of Band Physical Presence signal usage to determine NVMe Drive Presence Detect.

Enabled When the option is set to Enabled, Presence Detect is Inband LogicalOR OOB.
Disabled When the option is set to Disabled, only PCIe Inband Presence is used.

CPU Crash Log Support

This field controls Intel CPU Crash Log feature for collection of previous crash data from shared SRAM of Out-of-Band Management Services Module at post reset.

PCH Crash Log Support

Controls Intel PCH Crash Log feature for collection of previous crash data from PMC shared SRAM.

NVDIMM Mailbox In NFIT

The field controls publishing NVDIMM mailbox registers in NFIT structures.

For more information on the other buttons present in the Server Administrator Action pages, see Server Administrator Window Buttons.