Selection | View | Manage |
Processor UI | User, Power User, Administrator | Administrator |
BIOS Setup UI | Administrator | Administrator |
64-bit Support | Supports 64-bit. |
Hyperthreading (HT) | Intel's implementation of the simultaneous multithreading technology. |
Virtualization Technology (VT) | Intel's virtualization extension to the 64-bit x86 architecture. |
Demand Based Switching (DBS) | A power-management technology developed by Intel in which the applied voltage and clock speed for a microprocessor are kept to the minimum necessary to allow optimum performance of required operations. NOTE: Due to the limitations of the VMware® ESXi version 3.5 operating system on xx1x systems, the Demand Based Switching (DBS) field displays incorrect value. |
Execute Disable (XD) | Allows properly-written applications to mark off memory space as executable, so that code trying to access space above and beyond that will not be executed. |
Turbo Mode | Displays the processor capability. This is a processor capability that can increase the CPU frequency when the system is operating below the thermal, power or current limits. You can configure this processor capability under the BIOS setup page. |
Status | Indicates whether the cache on the processor is enabled or disabled. |
Level | Displays the cache level. Primary level cache (L1) is a very fast memory bank located near the processor execution units. Secondary level cache (L2) is a larger staging area that feeds the primary cache. Tertiary level cache (L3), if available, is an additional, larger memory bank which feeds data to the secondary cache. All of these cache levels are located in the processor. |
Max Size | Displays the maximum memory that the cache can occupy in KB. |
Installed Size | Displays the actual size of the cache. |
Type | Indicates whether the cache type is Data or Unified. |
Location | Indicates whether the cache is located on the processor or on a chip set outside the processor. |
Write Policy |
Describes how the cache deals with a write cycle.
In a Write-Back policy, the cache acts like a buffer. When
the processor starts a write cycle, the cache receives the data and stops
the cycle. The cache then writes the data back to main memory when the
system bus is available.
In a Write-Through policy, the processor writes through the
cache to main memory. The write cycle does not complete until the data is
stored into main memory.
If the write policy specifies Varies with Address, then the
policy is either write-back or write-through, according to the memory
address.
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Associativity |
Fully Associative cache allows any line in main memory to be
stored at any location in the cache.
16-Way Set-Associative cache directly maps sixteen specific
lines of memory to the same sixteen lines of cache.
8-Way Set-Associative cache directly maps eight specific
lines of memory to the same eight lines of cache.
4-Way Set-Associative cache directly maps four specific
lines of memory to the same four lines of cache.
3-Way Set-Associative cache directly maps three specific
lines of memory to the same three lines of cache.
2-Way Set-Associative cache directly maps two specific lines
of memory to the same two lines of cache.
1-Way Set-Associative cache directly maps a specific line of
memory in the same line of cache. For example, Line 0 of any page in memory
must be stored in Line 0 of cache memory.
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Error Correction Type | Identifies the type of error checking and correction (ECC) that this memory can perform. For example, single-bit ECC or multibit ECC. |
Go back to Processors Page | Returns to the previous window. |
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E-mails the contents of this window to your designated recipient. See the Server Administrator User's Guide for instructions about configuring your Simple Mail Transfer Protocol (SMTP) server. |
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Updates the screen with latest information. |
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Displays the online help for this page. |